Formated by GeSHi
library ieee;
 
use ieee.std_logic_1164.all;
 
use ieee.numeric_std.all;
 
 
 
entity timer64 is
 
 
 
  generic (
 
    D_WIDTH : integer := 64;
 
    T_WIDTH : integer := 32);
 
 
 
  port (
 
    clk       : in  std_logic;
 
    rst       : in  std_logic;
 
    start_in  : in  std_logic;
 
    timer_out : out std_logic_vector(D_WIDTH-1 downto 0)); 
 
 
 
end timer64;
 
 
 
architecture synth of timer64 is
 
 
 
  constant MAX_T : unsigned(T_WIDTH-1 downto 0) := (others => '1'); 
  signal   tovfl : unsigned(T_WIDTH-1 downto 0) := (others => '0');
 
  signal   tval  : unsigned(T_WIDTH-1 downto 0) := (others => '0');
 
 
 
  signal running : std_logic := '0';
 
 
 
begin
 
 
 
  start : process (clk, rst)
 
  begin
 
    if rst = '1' then
 
      running <= '0';
 
    elsif clk'event and clk = '1' then
 
      if start_in = '1' then
 
        running <= not running;
 
      end if;
 
    end if; end process start;
 
 
 
  count : process (clk, rst)
 
  begin
 
    if rst = '1' then
 
      timer_out <= (others => '0');
 
      tovfl     <= (others => '0');
 
      tval      <= (others => '0');
 
    elsif clk'event and clk = '1' then
 
      if running = '1' then
 
        tval      <= tval + 1;
 
        timer_out <= std_logic_vector(tovfl & tval);
 
        if tval = MAX_T then
 
          tovfl <= tovfl + 1;
 
          tval  <= (others => '0');
 
        end if;
 
      else
 
        tovfl <= (others => '0');
 
        tval  <= (others => '0');
 
      end if;
 
    end if;
 
  end process count;
 
 
 
end synth;
Parsed in 0.11765194 seconds